PMOS-switching dual-path charge pump in standard twin-well CMOS technology

In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-m twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7V under a 1.5V power supply and 20MHz clock frequency. It can supply a maximum load current of about 180 A. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at VDD=0.9V, approximately 10% higher peak power efficiency at VDD=1.5V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.