TY - GEN
T1 - Read disturb-free SRAM bit-cell for subthreshold memory applications
AU - Kim, Hyunmyoung
AU - Kim, Taehoon
AU - Manisankar, Sivasundar
AU - Chung, Yeonbae
N1 - Publisher Copyright:
© 2017 IEEE. All rights reserved.
PY - 2017/12/1
Y1 - 2017/12/1
N2 - In this work, we present a novel bit-cell which improves data stability in subthreshold SRAM operation. It consists of eight transistors, two of which cut off a positive feedback of cross-coupled inverters during the read access. In addition, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level during the dummy-read operation, and thus producing near-ideal voltage transfer characteristics essential for robust SRAM functionality. In the write access, the boosted wordline facilitates to change the contents of the memory bit. Implementation results in a 180 nm CMOS technology exhibit that the proposed cell remains unaffected by the read disturbance, while achieves 58.7 % higher dummy read stability and 3.68× better write-ability at 0.4 V supply compared to the standard 6T SRAM cell.
AB - In this work, we present a novel bit-cell which improves data stability in subthreshold SRAM operation. It consists of eight transistors, two of which cut off a positive feedback of cross-coupled inverters during the read access. In addition, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level during the dummy-read operation, and thus producing near-ideal voltage transfer characteristics essential for robust SRAM functionality. In the write access, the boosted wordline facilitates to change the contents of the memory bit. Implementation results in a 180 nm CMOS technology exhibit that the proposed cell remains unaffected by the read disturbance, while achieves 58.7 % higher dummy read stability and 3.68× better write-ability at 0.4 V supply compared to the standard 6T SRAM cell.
KW - 8T cell
KW - Data stability
KW - SRAM
KW - Subthreshold
UR - http://www.scopus.com/inward/record.url?scp=85043453119&partnerID=8YFLogxK
U2 - 10.1109/EDSSC.2017.8126401
DO - 10.1109/EDSSC.2017.8126401
M3 - Conference contribution
AN - SCOPUS:85043453119
T3 - EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits
SP - 1
EP - 2
BT - EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017
Y2 - 18 October 2017 through 20 October 2017
ER -