Reconfigurable array-based design for flexible cryptography chip architecture

Jeong Hun Jeong; Jeong O. Kim; Tae Yang Kim; Jun Rim Choi

doi:10.1109/PRIME.2017.7974178

Reconfigurable array-based design for flexible cryptography chip architecture

Jeong Hun Jeong, Jeong O. Kim, Tae Yang Kim, Jun Rim Choi

School of Electronics Engineering

Kyungpook National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, we present an area efficient crypto chip for sharing and selecting the hardware operation of the one public-key cipher and three block ciphers (ECC, AES, ARIA, and HIGHT) and reconfigurable crypto chip of an array-processor-based cryptography algorithm. Based on the proposed processor, we designed an encryption chip that reduced the total area of ECC, AES, ARIA and HIGHT by 21% using 0.18μm CMOS technology. Also, Cryptography Array Processor (CAP) of ECC, AES, ARIA, and HIGHT indicates high performance at 40Kbps, 1,085 Mbps, 746 Mbps and 175 Mbps respectively. The proposed design of crypto chip shows the reconfigurable flexibility of the encryption algorithm and high hardware performance.

Original language	English
Title of host publication	PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	345-348
Number of pages	4
ISBN (Electronic)	9781509065073
DOIs	https://doi.org/10.1109/PRIME.2017.7974178
State	Published - 10 Jul 2017
Event	13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017 - Giardini Naxos - Taormina, Italy Duration: 12 Jun 2017 → 15 Jun 2017

Publication series

Name	PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings

Conference

Conference	13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017
Country/Territory	Italy
City	Giardini Naxos - Taormina
Period	12/06/17 → 15/06/17

Keywords

array processor
block cipher
crypto chip
reconfigurable
S-box

Access to Document

10.1109/PRIME.2017.7974178

Cite this

Jeong, J. H., Kim, J. O., Kim, T. Y., & Choi, J. R. (2017). Reconfigurable array-based design for flexible cryptography chip architecture. In PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings (pp. 345-348). Article 7974178 (PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PRIME.2017.7974178

Jeong, Jeong Hun ; Kim, Jeong O. ; Kim, Tae Yang et al. / Reconfigurable array-based design for flexible cryptography chip architecture. PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 345-348 (PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings).

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title = "Reconfigurable array-based design for flexible cryptography chip architecture",

abstract = "In this paper, we present an area efficient crypto chip for sharing and selecting the hardware operation of the one public-key cipher and three block ciphers (ECC, AES, ARIA, and HIGHT) and reconfigurable crypto chip of an array-processor-based cryptography algorithm. Based on the proposed processor, we designed an encryption chip that reduced the total area of ECC, AES, ARIA and HIGHT by 21% using 0.18μm CMOS technology. Also, Cryptography Array Processor (CAP) of ECC, AES, ARIA, and HIGHT indicates high performance at 40Kbps, 1,085 Mbps, 746 Mbps and 175 Mbps respectively. The proposed design of crypto chip shows the reconfigurable flexibility of the encryption algorithm and high hardware performance.",

keywords = "array processor, block cipher, crypto chip, reconfigurable, S-box",

author = "Jeong, {Jeong Hun} and Kim, {Jeong O.} and Kim, {Tae Yang} and Choi, {Jun Rim}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017 ; Conference date: 12-06-2017 Through 15-06-2017",

year = "2017",

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doi = "10.1109/PRIME.2017.7974178",

language = "English",

series = "PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings",

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Jeong, JH, Kim, JO, Kim, TY & Choi, JR 2017, Reconfigurable array-based design for flexible cryptography chip architecture. in PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings., 7974178, PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 345-348, 13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017, Giardini Naxos - Taormina, Italy, 12/06/17. https://doi.org/10.1109/PRIME.2017.7974178

Reconfigurable array-based design for flexible cryptography chip architecture. / Jeong, Jeong Hun; Kim, Jeong O.; Kim, Tae Yang et al.
PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. p. 345-348 7974178 (PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - In this paper, we present an area efficient crypto chip for sharing and selecting the hardware operation of the one public-key cipher and three block ciphers (ECC, AES, ARIA, and HIGHT) and reconfigurable crypto chip of an array-processor-based cryptography algorithm. Based on the proposed processor, we designed an encryption chip that reduced the total area of ECC, AES, ARIA and HIGHT by 21% using 0.18μm CMOS technology. Also, Cryptography Array Processor (CAP) of ECC, AES, ARIA, and HIGHT indicates high performance at 40Kbps, 1,085 Mbps, 746 Mbps and 175 Mbps respectively. The proposed design of crypto chip shows the reconfigurable flexibility of the encryption algorithm and high hardware performance.

AB - In this paper, we present an area efficient crypto chip for sharing and selecting the hardware operation of the one public-key cipher and three block ciphers (ECC, AES, ARIA, and HIGHT) and reconfigurable crypto chip of an array-processor-based cryptography algorithm. Based on the proposed processor, we designed an encryption chip that reduced the total area of ECC, AES, ARIA and HIGHT by 21% using 0.18μm CMOS technology. Also, Cryptography Array Processor (CAP) of ECC, AES, ARIA, and HIGHT indicates high performance at 40Kbps, 1,085 Mbps, 746 Mbps and 175 Mbps respectively. The proposed design of crypto chip shows the reconfigurable flexibility of the encryption algorithm and high hardware performance.

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Jeong JH, Kim JO, Kim TY, Choi JR. Reconfigurable array-based design for flexible cryptography chip architecture. In PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. p. 345-348. 7974178. (PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings). doi: 10.1109/PRIME.2017.7974178

Reconfigurable array-based design for flexible cryptography chip architecture

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