Abstract
This letter presents a low-complexity semi-systolic array implementation for polynomial multiplication over GF(2m). We consider finite field Montgomery modular multiplication (MMM) based on two-level parallel computing approach to reduce the cell delay, latency, and area-time (AT) complexity. Compared to related multipliers, the proposed scheme yields significantly lower AT complexity.
| Original language | English |
|---|---|
| Article number | 20160797 |
| Journal | IEICE Electronics Express |
| Volume | 14 |
| Issue number | 17 |
| DOIs | |
| State | Published - 2017 |
Keywords
- Finite field arithmetic
- Modular multiplication
- Systolic array
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