Rigorous design and analysis of tunneling field-effect transistor with hetero-gate-dielectric and tunneling-boost n-layer

A gate-all-around tunneling field-effect transistor (GAA TFET) with local high-k gate-dielectric and tunneling-boost n-layer based on silicon is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (Ion) characteristics of TFETs. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (Lhigh-k) for the fixed nlayer length (Ln-layer). The simulation results have been analyzed in terms of on-and off-current (Ion and Ioff ), subthreshold swing (SS), and RF performances.