Scrambling technique of instruction power consumption for side-channel attack protection

This paper proposed the technique to protect the embedded devices from the timing analysis attack using a side-channel attack. Embedded devices have the advantage of excellent accessibility. However, because of the excellent accessibility, embedded devices are vulnerable to hardware attacks. In the case of the password matching function, the attacker can see the execution time of the function and infer which digits are matched monitoring the power consumption and using the timing analysis attack. In this paper, we proposed the clock scrambling method to hide the execution time of the instruction. It can help to protect embedded devices from the timing analysis attack by randomizing the execution time of the instruction. Our hardware model costs 2.56 % additional area for clock scrambler, and costs on average 28% in execution time and 27 % additional power consumption for scrambling power pattern.