Sequential design of a 8192 complex point FFT in OFDM receiver

Se Ho Park; Dong Hwan Kim; Dong Seog Han; Kyu Seon Lee; Sang Jin Park; Jun Rim Choi

doi:10.1109/APASIC.1999.824079

Sequential design of a 8192 complex point FFT in OFDM receiver

Se Ho Park, Dong Hwan Kim, Dong Seog Han, Kyu Seon Lee, Sang Jin Park, Jun Rim Choi

School of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

In this paper we propose an implementation method for a single-chip 8192 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 8 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 8192-point FFT consists of the cascaded blocks with six stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding. As a result the proposed structure brings about the 55% chip size reduction compared with conventional approach.

Original language	English
Title of host publication	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	262-265
Number of pages	4
ISBN (Print)	0780357051, 9780780357051
DOIs	https://doi.org/10.1109/APASIC.1999.824079
State	Published - 1999
Event	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of Duration: 23 Aug 1999 → 25 Aug 1999

Publication series

Name	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Conference

Conference	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
Country/Territory	Korea, Republic of
City	Seoul
Period	23/08/99 → 25/08/99

Access to Document

10.1109/APASIC.1999.824079

Cite this

Park, S. H., Kim, D. H., Han, D. S., Lee, K. S., Park, S. J., & Choi, J. R. (1999). Sequential design of a 8192 complex point FFT in OFDM receiver. In AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs (pp. 262-265). Article 824079 (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.1999.824079

@inproceedings{a6b251da4b0848e9849d1c1d0e7df487,

title = "Sequential design of a 8192 complex point FFT in OFDM receiver",

abstract = "In this paper we propose an implementation method for a single-chip 8192 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 8 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 8192-point FFT consists of the cascaded blocks with six stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding. As a result the proposed structure brings about the 55% chip size reduction compared with conventional approach.",

author = "Park, {Se Ho} and Kim, {Dong Hwan} and Han, {Dong Seog} and Lee, {Kyu Seon} and Park, {Sang Jin} and Choi, {Jun Rim}",

note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 ; Conference date: 23-08-1999 Through 25-08-1999",

year = "1999",

doi = "10.1109/APASIC.1999.824079",

language = "English",

isbn = "0780357051",

series = "AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "262--265",

booktitle = "AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs",

address = "United States",

}

Park, SH, Kim, DH, Han, DS, Lee, KS, Park, SJ & Choi, JR 1999, Sequential design of a 8192 complex point FFT in OFDM receiver. in AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs., 824079, AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs, Institute of Electrical and Electronics Engineers Inc., pp. 262-265, 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999, Seoul, Korea, Republic of, 23/08/99. https://doi.org/10.1109/APASIC.1999.824079

Sequential design of a 8192 complex point FFT in OFDM receiver. / Park, Se Ho; Kim, Dong Hwan; Han, Dong Seog et al.
AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs. Institute of Electrical and Electronics Engineers Inc., 1999. p. 262-265 824079 (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Sequential design of a 8192 complex point FFT in OFDM receiver

AU - Park, Se Ho

AU - Kim, Dong Hwan

AU - Han, Dong Seog

AU - Lee, Kyu Seon

AU - Park, Sang Jin

AU - Choi, Jun Rim

PY - 1999

Y1 - 1999

N2 - In this paper we propose an implementation method for a single-chip 8192 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 8 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 8192-point FFT consists of the cascaded blocks with six stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding. As a result the proposed structure brings about the 55% chip size reduction compared with conventional approach.

AB - In this paper we propose an implementation method for a single-chip 8192 complex point FFT in terms of sequential data processing. In order to reduce the required chip area for the sequential processing of 8 K complex data, a DRAM-like pipelined commutator architecture is used. The 16-point FFT is a basic building block of the entire FFT chip, and the 8192-point FFT consists of the cascaded blocks with six stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding. As a result the proposed structure brings about the 55% chip size reduction compared with conventional approach.

UR - http://www.scopus.com/inward/record.url?scp=85008008655&partnerID=8YFLogxK

U2 - 10.1109/APASIC.1999.824079

DO - 10.1109/APASIC.1999.824079

M3 - Conference contribution

AN - SCOPUS:85008008655

SN - 0780357051

SN - 9780780357051

T3 - AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

SP - 262

EP - 265

BT - AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999

Y2 - 23 August 1999 through 25 August 1999

ER -

Sequential design of a 8192 complex point FFT in OFDM receiver

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this