Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs

Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design and specification do not match, the CTS result will be wrong. Many users use licensed electronic design automation (EDA) tools like Synopsys, and Cadence to carry out accurate chip verification. However, when using a licensed EDA tool, it is difficult to change the function and confirm the overall process in detail. If the design is wrong, the expected cost is doubled, as it will be necessary to modify the design and check all processes for verification. Currently, it cannot check the synthesizability of the clock tree on the placement and route process using only RTL. The main purpose of this study is to predict the CTS result of pre-estimation roughly using an RTL source placing temporary logics using random buffer insertion before the route process: then the incorrectly designed part can be freely modified because the CTS result can be known in advance. Experimental results showed that this research achieves an increase in inserted buffer area by about 10%, the standard deviation of clock skew achieves zero clock skew after shallow CTS, and clock frequency increases by about 10%. This paper contributes to optimizing clock tree implementation by conducting the pre-route process before using the CTS tool. Also, our approach not only minimizes resource usage but also optimizes CTS for the RTL structure. It holds considerable value in enhancing the efficiency and performance of integrated circuits.