Simulation of CMOS logic inverter based on vertically stacked polycrystalline silicon nanosheet gate-all-around MOSFET and its electrical characteristics

So Ra Min, Sang Ho Lee, Jin Park, Geon Uk Kim, Ga Eon Kang, Jun Hyeok Heo, Young Jun Yoon, Jae Hwa Seo, Jaewon Jang, Jin Hyuk Bae, Sin Hyung Lee, In Man Kang

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

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