Single-Power-Supply Compatible Cryogenic In0.8Ga0.2As Quantum-well HEMTs with Record Combination of high-frequency and low-noise performance for quantum-computins applications

J. H. Yoo; Y. S. Jeon; S. W. Son; I. G. Lee; H. B. Jo; S. M. Choi; M. S. Yu; W. S. Park; H. J. Kim; H. J. Lee; S. P. Son; S. K. Kim; J. Yun; J. P. Shim; H. Jang; K. Lee; Y. Jeong; T. Kim; C. S. Shin; T. W. Kim; J. H. Lee; K. S. Seo; K. Yang; D. H. Kim

doi:10.1109/VLSITechnologyandCir46783.2024.10631365

Single-Power-Supply Compatible Cryogenic In_0.8Ga_0.2As Quantum-well HEMTs with Record Combination of high-frequency and low-noise performance for quantum-computins applications

J. H. Yoo
, Y. S. Jeon
, S. W. Son
, I. G. Lee
, H. B. Jo
, S. M. Choi
, M. S. Yu
, W. S. Park
, H. J. Kim
, H. J. Lee
, S. P. Son
, S. K. Kim
, J. Yun
, J. P. Shim
, H. Jang
, K. Lee
, Y. Jeong
, T. Kim
, C. S. Shin
, T. W. Kim

J. H. Lee, K. S. Seo, K. Yang, D. H. Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

We present L_g=45 nm E-mode cryogenic In 0sGa₀₂As quantum-well (QW) HEMTs with the record combination of high-frequency and low-noise characteristics. The fabricated devices exhibited a true E-mode operation, the best balance between f_T= 662 GHz and f_max= 653GHz, and the lowest √I_D/g_m=0.176 at 4 K. Besides, we investigated the temperature-dependent behavior. Three-layer model indicated that the reduction of ρ _barrier was critical to lower R_s at 4 K. According to the delay time analysis, the improvement of f_T was mainly due to the mitigation of the extrinsic channel charging delay, arising from the enhanced carrier transport at 4 K.

Original language	English
Title of host publication	2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350361469
DOIs	https://doi.org/10.1109/VLSITechnologyandCir46783.2024.10631365
State	Published - 2024
Event	2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024 - Honolulu, United States Duration: 16 Jun 2024 → 20 Jun 2024

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Conference

Conference	2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
Country/Territory	United States
City	Honolulu
Period	16/06/24 → 20/06/24

Access to Document

10.1109/VLSITechnologyandCir46783.2024.10631365

Cite this

Yoo, J. H., Jeon, Y. S., Son, S. W., Lee, I. G., Jo, H. B., Choi, S. M., Yu, M. S., Park, W. S., Kim, H. J., Lee, H. J., Son, S. P., Kim, S. K., Yun, J., Shim, J. P., Jang, H., Lee, K., Jeong, Y., Kim, T., Shin, C. S., ... Kim, D. H. (2024). Single-Power-Supply Compatible Cryogenic In_0.8Ga_0.2As Quantum-well HEMTs with Record Combination of high-frequency and low-noise performance for quantum-computins applications. In 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024 (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSITechnologyandCir46783.2024.10631365

Yoo, J. H. ; Jeon, Y. S. ; Son, S. W. et al. / Single-Power-Supply Compatible Cryogenic In_0.8Ga_0.2As Quantum-well HEMTs with Record Combination of high-frequency and low-noise performance for quantum-computins applications. 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024. Institute of Electrical and Electronics Engineers Inc., 2024. (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{091b6baf34144d129e077383ff5b888f,

title = "Single-Power-Supply Compatible Cryogenic In0.8Ga0.2As Quantum-well HEMTs with Record Combination of high-frequency and low-noise performance for quantum-computins applications",

abstract = "We present Lg=45 nm E-mode cryogenic In 0sGa02As quantum-well (QW) HEMTs with the record combination of high-frequency and low-noise characteristics. The fabricated devices exhibited a true E-mode operation, the best balance between fT= 662 GHz and fmax= 653GHz, and the lowest √ID/gm=0.176 at 4 K. Besides, we investigated the temperature-dependent behavior. Three-layer model indicated that the reduction of ρ barrier was critical to lower Rs at 4 K. According to the delay time analysis, the improvement of fT was mainly due to the mitigation of the extrinsic channel charging delay, arising from the enhanced carrier transport at 4 K.",

author = "Yoo, \{J. H.\} and Jeon, \{Y. S.\} and Son, \{S. W.\} and Lee, \{I. G.\} and Jo, \{H. B.\} and Choi, \{S. M.\} and Yu, \{M. S.\} and Park, \{W. S.\} and Kim, \{H. J.\} and Lee, \{H. J.\} and Son, \{S. P.\} and Kim, \{S. K.\} and J. Yun and Shim, \{J. P.\} and H. Jang and K. Lee and Y. Jeong and T. Kim and Shin, \{C. S.\} and Kim, \{T. W.\} and Lee, \{J. H.\} and Seo, \{K. S.\} and K. Yang and Kim, \{D. H.\}",

note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024 ; Conference date: 16-06-2024 Through 20-06-2024",

year = "2024",

doi = "10.1109/VLSITechnologyandCir46783.2024.10631365",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024",

address = "United States",

}

Yoo, JH, Jeon, YS, Son, SW, Lee, IG, Jo, HB, Choi, SM, Yu, MS, Park, WS, Kim, HJ, Lee, HJ, Son, SP, Kim, SK, Yun, J, Shim, JP, Jang, H, Lee, K, Jeong, Y, Kim, T, Shin, CS, Kim, TW, Lee, JH, Seo, KS, Yang, K & Kim, DH 2024, Single-Power-Supply Compatible Cryogenic In_0.8Ga_0.2As Quantum-well HEMTs with Record Combination of high-frequency and low-noise performance for quantum-computins applications. in 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024. Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers Inc., 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024, Honolulu, United States, 16/06/24. https://doi.org/10.1109/VLSITechnologyandCir46783.2024.10631365

Single-Power-Supply Compatible Cryogenic In_0.8Ga_0.2As Quantum-well HEMTs with Record Combination of high-frequency and low-noise performance for quantum-computins applications. / Yoo, J. H.; Jeon, Y. S.; Son, S. W. et al.
2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024. Institute of Electrical and Electronics Engineers Inc., 2024. (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Yoo, J. H.

AU - Jeon, Y. S.

AU - Son, S. W.

AU - Lee, I. G.

AU - Jo, H. B.

AU - Choi, S. M.

AU - Yu, M. S.

AU - Park, W. S.

AU - Kim, H. J.

AU - Lee, H. J.

AU - Son, S. P.

AU - Kim, S. K.

AU - Yun, J.

AU - Shim, J. P.

AU - Jang, H.

AU - Lee, K.

AU - Jeong, Y.

AU - Kim, T.

AU - Shin, C. S.

AU - Kim, T. W.

AU - Lee, J. H.

AU - Seo, K. S.

AU - Yang, K.

AU - Kim, D. H.

PY - 2024

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N2 - We present Lg=45 nm E-mode cryogenic In 0sGa02As quantum-well (QW) HEMTs with the record combination of high-frequency and low-noise characteristics. The fabricated devices exhibited a true E-mode operation, the best balance between fT= 662 GHz and fmax= 653GHz, and the lowest √ID/gm=0.176 at 4 K. Besides, we investigated the temperature-dependent behavior. Three-layer model indicated that the reduction of ρ barrier was critical to lower Rs at 4 K. According to the delay time analysis, the improvement of fT was mainly due to the mitigation of the extrinsic channel charging delay, arising from the enhanced carrier transport at 4 K.

AB - We present Lg=45 nm E-mode cryogenic In 0sGa02As quantum-well (QW) HEMTs with the record combination of high-frequency and low-noise characteristics. The fabricated devices exhibited a true E-mode operation, the best balance between fT= 662 GHz and fmax= 653GHz, and the lowest √ID/gm=0.176 at 4 K. Besides, we investigated the temperature-dependent behavior. Three-layer model indicated that the reduction of ρ barrier was critical to lower Rs at 4 K. According to the delay time analysis, the improvement of fT was mainly due to the mitigation of the extrinsic channel charging delay, arising from the enhanced carrier transport at 4 K.

UR - https://www.scopus.com/pages/publications/85203588622

U2 - 10.1109/VLSITechnologyandCir46783.2024.10631365

DO - 10.1109/VLSITechnologyandCir46783.2024.10631365

M3 - Conference contribution

AN - SCOPUS:85203588622

T3 - Digest of Technical Papers - Symposium on VLSI Technology

BT - 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024

Y2 - 16 June 2024 through 20 June 2024

ER -

Yoo JH, Jeon YS, Son SW, Lee IG, Jo HB, Choi SM et al. Single-Power-Supply Compatible Cryogenic In_0.8Ga_0.2As Quantum-well HEMTs with Record Combination of high-frequency and low-noise performance for quantum-computins applications. In 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024. Institute of Electrical and Electronics Engineers Inc. 2024. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSITechnologyandCir46783.2024.10631365