TY - GEN
T1 - Speed-Area-Power Efficient Ternary Logic Gate Implementation Based on Typical MOS Transistors
AU - Jeon, Gihyeon
AU - Park, Daejin
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Previous papers have focused solely on designing ternary logic gates or constructing adders using predesigned ternary logic gates. However, this paper takes a novel approach by designing ternary logic gates using typical MOSFETs and employs them to construct a ripple carry adder. Furthermore, this paper conducts a comprehensive comparison between the resulting ripple carry adder and binary ripple carry adder in terms of speed, power(energy) consumption, and area. This paper demonstrates that the ternary adder designed by the author, using PSpice and Verilog with VPI, can exhibit differences 75% compared to the conventional binary adder.
AB - Previous papers have focused solely on designing ternary logic gates or constructing adders using predesigned ternary logic gates. However, this paper takes a novel approach by designing ternary logic gates using typical MOSFETs and employs them to construct a ripple carry adder. Furthermore, this paper conducts a comprehensive comparison between the resulting ripple carry adder and binary ripple carry adder in terms of speed, power(energy) consumption, and area. This paper demonstrates that the ternary adder designed by the author, using PSpice and Verilog with VPI, can exhibit differences 75% compared to the conventional binary adder.
KW - area
KW - power(energy) consumption
KW - speed
KW - ternary logic gates
KW - ternary ripple carry adder
UR - https://www.scopus.com/pages/publications/85189248098
U2 - 10.1109/ICEIC61013.2024.10457139
DO - 10.1109/ICEIC61013.2024.10457139
M3 - Conference contribution
AN - SCOPUS:85189248098
T3 - 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024
BT - 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024
Y2 - 28 January 2024 through 31 January 2024
ER -
