Abstract
Previous papers have focused solely on designing ternary logic gates or constructing adders using predesigned ternary logic gates. However, this paper takes a novel approach by designing ternary logic gates using typical MOSFETs and employs them to construct a ripple carry adder. Furthermore, this paper conducts a comprehensive comparison between the resulting ripple carry adder and binary ripple carry adder in terms of speed, power(energy) consumption, and area. This paper demonstrates that the ternary adder designed by the author, using PSpice and Verilog with VPI, can exhibit differences 75% compared to the conventional binary adder.
| Original language | English |
|---|---|
| Title of host publication | 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9798350371888 |
| DOIs | |
| State | Published - 2024 |
| Event | 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024 - Taipei, Taiwan, Province of China Duration: 28 Jan 2024 → 31 Jan 2024 |
Publication series
| Name | 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024 |
|---|
Conference
| Conference | 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024 |
|---|---|
| Country/Territory | Taiwan, Province of China |
| City | Taipei |
| Period | 28/01/24 → 31/01/24 |
UN SDGs
This output contributes to the following UN Sustainable Development Goals (SDGs)
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SDG 7 Affordable and Clean Energy
Keywords
- area
- power(energy) consumption
- speed
- ternary logic gates
- ternary ripple carry adder
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