Structured design of a 288-tap FIR filter by optimized partial product tree compression

A compact 10-b. 288-tap finite impulse response (FIR) filter is designed by adopting structured architecture that employs an optimized partial product tree compression method. The new scheme is based on the addition of equally weighted partial products resulted from 288 multiplications of the filter coefficients and the inputs. The 288 multiplication and 287 addition operations are decomposed to add 1440 partial products and the sign extension operations are manipulated independently to ensure the operation at 72 MHz, the internal clock frequency generated by the integrated phase-locked loop (PLL) clock multiplier. In addition to the optimized transmission gate full adder, modified carry save compression circuits such as 4:2 and 5:5:2 compressors are used to perform decomposed partial product addition. This structured approach enables cascade design that requires more than 288-tap FIR filtering. The completed 288-tap FIR filter core occupies 5.36× 7.29 mm ² of silicon area that consists of 371 732 transistors in 0.6-μm triple-metal CMOS technology, and it consumes only 0.8 W of average power at 3.3 V.