Abstract
A compact 10-bit, 288-tap FIR filter is designed by adopting structured architecture which employs optimized partial product tree compression method. The new architecture is based on the addition of equally weighted partial products which result from 288 multiplications of the filter coefficients and the inputs. The 288 multiplication and 287 addition operations are decomposed to add 1440 partial products to meet the tight timing requirement. Optimized parallel compression schemes such as 4:2 and 5:5:2 compressors are used to perform decomposed partial product addition. The completed 288-tap FIR filter occupies 7×9mm2 of Silicon area which consists of 385754 transistors in 0.6μm triple-metal CMOS technology.
| Original language | English |
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| Pages (from-to) | 79-82 |
| Number of pages | 4 |
| Journal | Proceedings of the Custom Integrated Circuits Conference |
| State | Published - 1996 |
| Event | Proceedings of the 1996 IEEE Custom Integrated Circuits Conference - San Diego, CA, USA Duration: 5 May 1996 → 8 May 1996 |