Tcl-based Simulation Platform for Light-weight ResNet Implementation

Seunghyun Park; Dongkyu Lee; Daejin Park

doi:10.1109/ISOCC59558.2023.10396397

Tcl-based Simulation Platform for Light-weight ResNet Implementation

Seunghyun Park, Dongkyu Lee, Daejin Park

School of Electronics Engineering

Kyungpook National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The growing computational cost and size of artificial intelligence have led to a need for hardware accelerators. However, training times for neural networks remain a significant obstacle, leading to increased simulation times and decreased productivity. In this paper, we propose a runtime layer replaceable simulation platform using a depth-reduction algorithm. The proposed platform generates weights optimized for various ResNet depths using the first trained high-depth weights. This platform can reduce simulation time by reducing the number of trainings without significantly degrading the inference accuracy.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2023, ISOCC 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	335-336
Number of pages	2
ISBN (Electronic)	9798350327038
DOIs	https://doi.org/10.1109/ISOCC59558.2023.10396397
State	Published - 2023
Event	20th International SoC Design Conference, ISOCC 2023 - Jeju, Korea, Republic of Duration: 25 Oct 2023 → 28 Oct 2023

Publication series

Name	Proceedings - International SoC Design Conference 2023, ISOCC 2023

Conference

Conference	20th International SoC Design Conference, ISOCC 2023
Country/Territory	Korea, Republic of
City	Jeju
Period	25/10/23 → 28/10/23

Keywords

Depthreduction algorithm
ResNet Optimization
Tcl-based simulation

Access to Document

10.1109/ISOCC59558.2023.10396397

Cite this

@inproceedings{cbc787e4664a4e25934666763183a1a9,

title = "Tcl-based Simulation Platform for Light-weight ResNet Implementation",

abstract = "The growing computational cost and size of artificial intelligence have led to a need for hardware accelerators. However, training times for neural networks remain a significant obstacle, leading to increased simulation times and decreased productivity. In this paper, we propose a runtime layer replaceable simulation platform using a depth-reduction algorithm. The proposed platform generates weights optimized for various ResNet depths using the first trained high-depth weights. This platform can reduce simulation time by reducing the number of trainings without significantly degrading the inference accuracy.",

keywords = "Depthreduction algorithm, ResNet Optimization, Tcl-based simulation",

author = "Seunghyun Park and Dongkyu Lee and Daejin Park",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 20th International SoC Design Conference, ISOCC 2023 ; Conference date: 25-10-2023 Through 28-10-2023",

year = "2023",

doi = "10.1109/ISOCC59558.2023.10396397",

language = "English",

series = "Proceedings - International SoC Design Conference 2023, ISOCC 2023",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "335--336",

booktitle = "Proceedings - International SoC Design Conference 2023, ISOCC 2023",

address = "United States",

}

Park, S, Lee, D & Park, D 2023, Tcl-based Simulation Platform for Light-weight ResNet Implementation. in Proceedings - International SoC Design Conference 2023, ISOCC 2023. Proceedings - International SoC Design Conference 2023, ISOCC 2023, Institute of Electrical and Electronics Engineers Inc., pp. 335-336, 20th International SoC Design Conference, ISOCC 2023, Jeju, Korea, Republic of, 25/10/23. https://doi.org/10.1109/ISOCC59558.2023.10396397

Tcl-based Simulation Platform for Light-weight ResNet Implementation. / Park, Seunghyun; Lee, Dongkyu; Park, Daejin.
Proceedings - International SoC Design Conference 2023, ISOCC 2023. Institute of Electrical and Electronics Engineers Inc., 2023. p. 335-336 (Proceedings - International SoC Design Conference 2023, ISOCC 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Tcl-based Simulation Platform for Light-weight ResNet Implementation

AU - Park, Seunghyun

AU - Lee, Dongkyu

AU - Park, Daejin

PY - 2023

Y1 - 2023

N2 - The growing computational cost and size of artificial intelligence have led to a need for hardware accelerators. However, training times for neural networks remain a significant obstacle, leading to increased simulation times and decreased productivity. In this paper, we propose a runtime layer replaceable simulation platform using a depth-reduction algorithm. The proposed platform generates weights optimized for various ResNet depths using the first trained high-depth weights. This platform can reduce simulation time by reducing the number of trainings without significantly degrading the inference accuracy.

AB - The growing computational cost and size of artificial intelligence have led to a need for hardware accelerators. However, training times for neural networks remain a significant obstacle, leading to increased simulation times and decreased productivity. In this paper, we propose a runtime layer replaceable simulation platform using a depth-reduction algorithm. The proposed platform generates weights optimized for various ResNet depths using the first trained high-depth weights. This platform can reduce simulation time by reducing the number of trainings without significantly degrading the inference accuracy.

KW - Depthreduction algorithm

KW - ResNet Optimization

KW - Tcl-based simulation

UR - http://www.scopus.com/inward/record.url?scp=85184804163&partnerID=8YFLogxK

U2 - 10.1109/ISOCC59558.2023.10396397

DO - 10.1109/ISOCC59558.2023.10396397

M3 - Conference contribution

AN - SCOPUS:85184804163

T3 - Proceedings - International SoC Design Conference 2023, ISOCC 2023

SP - 335

EP - 336

BT - Proceedings - International SoC Design Conference 2023, ISOCC 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 20th International SoC Design Conference, ISOCC 2023

Y2 - 25 October 2023 through 28 October 2023

ER -

Tcl-based Simulation Platform for Light-weight ResNet Implementation

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this