TY - GEN
T1 - Ternary Competitive to Binary
T2 - 52nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2022
AU - Lee, Hyundong
AU - Jang, Hyeseung
AU - Yun, Jihyeong
AU - Jin, Huijeen
AU - Kim, Jongbeom
AU - Kim, Yeji
AU - Song, Taigon
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - As the development of binary systems forecasted to reach to its end, ternary system is gaining more attention. However, most ternary logic circuits were not considered to be a 'true' competitor to binary systems. To counter this common belief on ternary logic, in this study, we propose a ternary logic system based on depletion-mode MOSFETs and conventional MOSFETs that can truly compete with binary systems in terms of power and delay. Based on our novel circuitry of 11 logic gates, we illustrate that (1) our circuits consume near-zero static current on all logic states (-1, 0, +1), (2) our standard ternary inverter (STI) shows improved PDP of 71× and 245× compared to conventional CNTFET or memristor and MOSFET based ternary circuits, and (3) our balanced ternary full adder (BTFA) shows 48× improved power consumption compared to other ternary-device based adders and 5.3× improved power compared to the same devices. With our results, we highlight that ternary logic is now competitive to binary.
AB - As the development of binary systems forecasted to reach to its end, ternary system is gaining more attention. However, most ternary logic circuits were not considered to be a 'true' competitor to binary systems. To counter this common belief on ternary logic, in this study, we propose a ternary logic system based on depletion-mode MOSFETs and conventional MOSFETs that can truly compete with binary systems in terms of power and delay. Based on our novel circuitry of 11 logic gates, we illustrate that (1) our circuits consume near-zero static current on all logic states (-1, 0, +1), (2) our standard ternary inverter (STI) shows improved PDP of 71× and 245× compared to conventional CNTFET or memristor and MOSFET based ternary circuits, and (3) our balanced ternary full adder (BTFA) shows 48× improved power consumption compared to other ternary-device based adders and 5.3× improved power compared to the same devices. With our results, we highlight that ternary logic is now competitive to binary.
KW - balanced ternary full adder
KW - Depletion-mode MOSFET
KW - ternary logic
UR - http://www.scopus.com/inward/record.url?scp=85133469021&partnerID=8YFLogxK
U2 - 10.1109/ISMVL52857.2022.00011
DO - 10.1109/ISMVL52857.2022.00011
M3 - Conference contribution
AN - SCOPUS:85133469021
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 21
EP - 26
BT - Proceedings - 2022 IEEE 52nd International Symposium on Multiple-Valued Logic, ISMVL 2022
PB - IEEE Computer Society
Y2 - 18 May 2022 through 20 May 2022
ER -