Ternary full adder using multi-threshold voltage graphene barristors

Sunwoo Heo; Sunmean Kim; Kiyung Kim; Hyeji Lee; So Young Kim; Yun Ji Kim; Seung Mo Kim; Ho In Lee; Segi Lee; Kyung Rok Kim; Seokhyeong Kang; Byoung Hun Lee

doi:10.1109/LED.2018.2874055

Ternary full adder using multi-threshold voltage graphene barristors

Sunwoo Heo
, Sunmean Kim
, Kiyung Kim
, Hyeji Lee
, So Young Kim
, Yun Ji Kim
, Seung Mo Kim
, Ho In Lee
, Segi Lee
, Kyung Rok Kim
, Seokhyeong Kang
, Byoung Hun Lee

Gwangju Institute of Science and Technology
Ulsan National Institute of Science and Technology
Pohang University of Science and Technology

Research output: Contribution to journal › Article › peer-review

55 Scopus citations

Abstract

Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of 10^-16 J, which is comparable to the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-V_th ternary graphene barristors.

Original language	English
Article number	8482320
Pages (from-to)	1948-1951
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	39
Issue number	12
DOIs	https://doi.org/10.1109/LED.2018.2874055
State	Published - Dec 2018

Keywords

Graphene barristor
multi threshold voltage ternary graphene barristor
ternary full adder
ternary logic

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10.1109/LED.2018.2874055

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title = "Ternary full adder using multi-threshold voltage graphene barristors",

abstract = "Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of 10-16 J, which is comparable to the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors.",

keywords = "Graphene barristor, multi threshold voltage ternary graphene barristor, ternary full adder, ternary logic",

author = "Sunwoo Heo and Sunmean Kim and Kiyung Kim and Hyeji Lee and Kim, \{So Young\} and Kim, \{Yun Ji\} and Kim, \{Seung Mo\} and Lee, \{Ho In\} and Segi Lee and Kim, \{Kyung Rok\} and Seokhyeong Kang and Lee, \{Byoung Hun\}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.",

year = "2018",

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doi = "10.1109/LED.2018.2874055",

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T1 - Ternary full adder using multi-threshold voltage graphene barristors

AU - Heo, Sunwoo

AU - Kim, Sunmean

AU - Kim, Kiyung

AU - Lee, Hyeji

AU - Kim, So Young

AU - Kim, Yun Ji

AU - Kim, Seung Mo

AU - Lee, Ho In

AU - Lee, Segi

AU - Kim, Kyung Rok

AU - Kang, Seokhyeong

AU - Lee, Byoung Hun

PY - 2018/12

Y1 - 2018/12

N2 - Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of 10-16 J, which is comparable to the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors.

AB - Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of 10-16 J, which is comparable to the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors.

KW - Graphene barristor

KW - multi threshold voltage ternary graphene barristor

KW - ternary full adder

KW - ternary logic

UR - https://www.scopus.com/pages/publications/85054505467

U2 - 10.1109/LED.2018.2874055

DO - 10.1109/LED.2018.2874055

M3 - Article

AN - SCOPUS:85054505467

SN - 0741-3106

VL - 39

SP - 1948

EP - 1951

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 12

M1 - 8482320

ER -

Ternary full adder using multi-threshold voltage graphene barristors

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Keywords

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