Ternary Sense Amplifier Design for Ternary SRAM

Minjeong Choi; Youngchang Choi; Sunmean Kim; Seokhyeong Kang

doi:10.1109/ISOCC53507.2021.9613911

Ternary Sense Amplifier Design for Ternary SRAM

Minjeong Choi, Youngchang Choi, Sunmean Kim, Seokhyeong Kang

School of Electronics Engineering

Pohang University of Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper proposes the design of a Ternary Sense Amplifier (T-SA) using Samsung-28nm fabrication process that can sense three states, which are VDD, VDD/2, and GND. The T-SA has a ternary inverter back-To-back structure, and is configured as a latch type. The trade-off relationship between sensing margin and sensing speed was analyzed according to the size. The T-SA may enable the realization of a memory array with ternary logic in a Multi-Valued Logic system.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2021, ISOCC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	151-152
Number of pages	2
ISBN (Electronic)	9781665401746
DOIs	https://doi.org/10.1109/ISOCC53507.2021.9613911
State	Published - 2021
Event	18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of Duration: 6 Oct 2021 → 9 Oct 2021

Publication series

Name	Proceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference	18th International System-on-Chip Design Conference, ISOCC 2021
Country/Territory	Korea, Republic of
City	Jeju Island
Period	6/10/21 → 9/10/21

Keywords

Multi-Valued Logic
Sense Amplifier
Ternary SRAM

Access to Document

10.1109/ISOCC53507.2021.9613911

Cite this

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title = "Ternary Sense Amplifier Design for Ternary SRAM",

abstract = "This paper proposes the design of a Ternary Sense Amplifier (T-SA) using Samsung-28nm fabrication process that can sense three states, which are VDD, VDD/2, and GND. The T-SA has a ternary inverter back-To-back structure, and is configured as a latch type. The trade-off relationship between sensing margin and sensing speed was analyzed according to the size. The T-SA may enable the realization of a memory array with ternary logic in a Multi-Valued Logic system.",

keywords = "Multi-Valued Logic, Sense Amplifier, Ternary SRAM",

author = "Minjeong Choi and Youngchang Choi and Sunmean Kim and Seokhyeong Kang",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 18th International System-on-Chip Design Conference, ISOCC 2021 ; Conference date: 06-10-2021 Through 09-10-2021",

year = "2021",

doi = "10.1109/ISOCC53507.2021.9613911",

language = "English",

series = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "151--152",

booktitle = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

address = "United States",

}

Choi, M, Choi, Y, Kim, S & Kang, S 2021, Ternary Sense Amplifier Design for Ternary SRAM. in Proceedings - International SoC Design Conference 2021, ISOCC 2021. Proceedings - International SoC Design Conference 2021, ISOCC 2021, Institute of Electrical and Electronics Engineers Inc., pp. 151-152, 18th International System-on-Chip Design Conference, ISOCC 2021, Jeju Island, Korea, Republic of, 6/10/21. https://doi.org/10.1109/ISOCC53507.2021.9613911

Ternary Sense Amplifier Design for Ternary SRAM. / Choi, Minjeong; Choi, Youngchang; Kim, Sunmean et al.
Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 151-152 (Proceedings - International SoC Design Conference 2021, ISOCC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Ternary Sense Amplifier Design for Ternary SRAM

AU - Choi, Minjeong

AU - Choi, Youngchang

AU - Kim, Sunmean

AU - Kang, Seokhyeong

PY - 2021

Y1 - 2021

N2 - This paper proposes the design of a Ternary Sense Amplifier (T-SA) using Samsung-28nm fabrication process that can sense three states, which are VDD, VDD/2, and GND. The T-SA has a ternary inverter back-To-back structure, and is configured as a latch type. The trade-off relationship between sensing margin and sensing speed was analyzed according to the size. The T-SA may enable the realization of a memory array with ternary logic in a Multi-Valued Logic system.

AB - This paper proposes the design of a Ternary Sense Amplifier (T-SA) using Samsung-28nm fabrication process that can sense three states, which are VDD, VDD/2, and GND. The T-SA has a ternary inverter back-To-back structure, and is configured as a latch type. The trade-off relationship between sensing margin and sensing speed was analyzed according to the size. The T-SA may enable the realization of a memory array with ternary logic in a Multi-Valued Logic system.

KW - Multi-Valued Logic

KW - Sense Amplifier

KW - Ternary SRAM

UR - http://www.scopus.com/inward/record.url?scp=85123342833&partnerID=8YFLogxK

U2 - 10.1109/ISOCC53507.2021.9613911

DO - 10.1109/ISOCC53507.2021.9613911

M3 - Conference contribution

AN - SCOPUS:85123342833

T3 - Proceedings - International SoC Design Conference 2021, ISOCC 2021

SP - 151

EP - 152

BT - Proceedings - International SoC Design Conference 2021, ISOCC 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 18th International System-on-Chip Design Conference, ISOCC 2021

Y2 - 6 October 2021 through 9 October 2021

ER -

Ternary Sense Amplifier Design for Ternary SRAM

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Keywords

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