The impact of 3D stacking and technology scaling on the power and area of stereo matching processors

Seung Ho Ok, Yong Hwan Lee, Jae Hoon Shim, Sung Kyu Lim, Byungin Moon

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.

Original languageEnglish
Article number426
JournalSensors
Volume17
Issue number2
DOIs
StatePublished - 22 Feb 2017

Keywords

  • Low-power
  • Stereo matching processor
  • Technology scaling
  • Through-silicon via

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