The impact of side-recess spacing on the logic performance of 50 nm in _0.7Ga_0.3As HEMTs

We are investigating InGaAs HEMTs as a future high-speed, low-power logic technology for beyond CMOS applications. In this work, we have experimentally studied the role of the siderecess spacing (L_side) on the logic performance of 50 nm In_0.7Ga_0.3As HEMTs. We have found that L_side has a large impact on electrostatic integrity (short channel effects), gate leakage current, gate-drain capacitance, and source and drain resistance. For our device design, an optimum value of L_side of 150 nm is found. 50 nm In_0.7Ga_0.3As HEMTs with this value of L_side exhibit I_ON/I_OFF ratios in excess of 10⁴, subthreshold slopes smaller than 90 mV/dec, and logic gate delays of about 1.3 ps at a V_cc of 0.5 V. In spite of the fact that these devices are not optimized for logic, these values are comparable to state-of-the-art MOSFETs of similar gate lengths. Our work shows that in the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs HEMTs hold considerable promise.