Three-tier 3D ICs for more power reduction: Strategies in CAD, design, and bonding selection

Taigon Song; Shreepad Panth; Yoo Jin Chae; Sung Kyu Lim

doi:10.1109/ICCAD.2015.7372645

Three-tier 3D ICs for more power reduction: Strategies in CAD, design, and bonding selection

Taigon Song, Shreepad Panth, Yoo Jin Chae, Sung Kyu Lim

School of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

Low-power is one of the key driving forces in modern VLSI systems. Several recent studies show that 3D ICs offer significant power savings over 2D ICs, primarily due to wirelength and buffer saving. However, these existing studies are mainly limited to 2-tier designs. In this paper, our target is extended to 3-tier 3D ICs. Our study first shows that the one additional tier available in 3-tier 3D ICs does offer more power saving compared with their 2-tier 3D IC counterparts, but more careful floorplanning, through-silicon via (TSV) management, and block folding considerations are required. Second, we find that the three tiers can be bonded in different ways: (1) face-to-back only and (2) face-to-face and face-to-back combined. Our study shows that these choices pose additional challenges in design optimizations for more power saving. Lastly, we develop effective CAD solutions that are seamlessly integrated into commercial 2D IC tools to handle 3-tier 3D IC power optimization under various bonding style options. With our low-power design methods combined, our 3-tier 3D ICs provide -14.8% more power reduction over 2-tier 3D ICs and -36.0% over 2D ICs under the same performance.

Original language	English
Title of host publication	2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	752-757
Number of pages	6
ISBN (Electronic)	9781467383882
DOIs	https://doi.org/10.1109/ICCAD.2015.7372645
State	Published - 5 Jan 2016
Event	34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 - Austin, United States Duration: 2 Nov 2015 → 6 Nov 2015

Publication series

Name	2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015

Conference

Conference	34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015
Country/Territory	United States
City	Austin
Period	2/11/15 → 6/11/15

Keywords

3D IC
F2F
TSV
low power

Access to Document

10.1109/ICCAD.2015.7372645

Cite this

Song, T., Panth, S., Chae, Y. J., & Lim, S. K. (2016). Three-tier 3D ICs for more power reduction: Strategies in CAD, design, and bonding selection. In 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 (pp. 752-757). Article 7372645 (2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCAD.2015.7372645

Song, Taigon ; Panth, Shreepad ; Chae, Yoo Jin et al. / Three-tier 3D ICs for more power reduction : Strategies in CAD, design, and bonding selection. 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 752-757 (2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015).

@inproceedings{8a3585c105a34ac1afc60d1364e43c49,

title = "Three-tier 3D ICs for more power reduction: Strategies in CAD, design, and bonding selection",

abstract = "Low-power is one of the key driving forces in modern VLSI systems. Several recent studies show that 3D ICs offer significant power savings over 2D ICs, primarily due to wirelength and buffer saving. However, these existing studies are mainly limited to 2-tier designs. In this paper, our target is extended to 3-tier 3D ICs. Our study first shows that the one additional tier available in 3-tier 3D ICs does offer more power saving compared with their 2-tier 3D IC counterparts, but more careful floorplanning, through-silicon via (TSV) management, and block folding considerations are required. Second, we find that the three tiers can be bonded in different ways: (1) face-to-back only and (2) face-to-face and face-to-back combined. Our study shows that these choices pose additional challenges in design optimizations for more power saving. Lastly, we develop effective CAD solutions that are seamlessly integrated into commercial 2D IC tools to handle 3-tier 3D IC power optimization under various bonding style options. With our low-power design methods combined, our 3-tier 3D ICs provide -14.8% more power reduction over 2-tier 3D ICs and -36.0% over 2D ICs under the same performance.",

keywords = "3D IC, F2F, TSV, low power",

author = "Taigon Song and Shreepad Panth and Chae, {Yoo Jin} and Lim, {Sung Kyu}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 ; Conference date: 02-11-2015 Through 06-11-2015",

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Song, T, Panth, S, Chae, YJ & Lim, SK 2016, Three-tier 3D ICs for more power reduction: Strategies in CAD, design, and bonding selection. in 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015., 7372645, 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015, Institute of Electrical and Electronics Engineers Inc., pp. 752-757, 34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015, Austin, United States, 2/11/15. https://doi.org/10.1109/ICCAD.2015.7372645

Three-tier 3D ICs for more power reduction: Strategies in CAD, design, and bonding selection. / Song, Taigon; Panth, Shreepad; Chae, Yoo Jin et al.
2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc., 2016. p. 752-757 7372645 (2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Low-power is one of the key driving forces in modern VLSI systems. Several recent studies show that 3D ICs offer significant power savings over 2D ICs, primarily due to wirelength and buffer saving. However, these existing studies are mainly limited to 2-tier designs. In this paper, our target is extended to 3-tier 3D ICs. Our study first shows that the one additional tier available in 3-tier 3D ICs does offer more power saving compared with their 2-tier 3D IC counterparts, but more careful floorplanning, through-silicon via (TSV) management, and block folding considerations are required. Second, we find that the three tiers can be bonded in different ways: (1) face-to-back only and (2) face-to-face and face-to-back combined. Our study shows that these choices pose additional challenges in design optimizations for more power saving. Lastly, we develop effective CAD solutions that are seamlessly integrated into commercial 2D IC tools to handle 3-tier 3D IC power optimization under various bonding style options. With our low-power design methods combined, our 3-tier 3D ICs provide -14.8% more power reduction over 2-tier 3D ICs and -36.0% over 2D ICs under the same performance.

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M3 - Conference contribution

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Song T, Panth S, Chae YJ, Lim SK. Three-tier 3D ICs for more power reduction: Strategies in CAD, design, and bonding selection. In 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc. 2016. p. 752-757. 7372645. (2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015). doi: 10.1109/ICCAD.2015.7372645

Three-tier 3D ICs for more power reduction: Strategies in CAD, design, and bonding selection

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Keywords

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