Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity

Bon Woong Ku, Taigon Song, Arthur Nieuwoudt, Sung Kyu Lim

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

Existing transistor-level monolithic 3D (T-M3D) standard cell layouts are based on the folding scheme, in which the pull-down network is simply folded and placed on top of the pull-up network. In this paper, we propose a new layout method, the stitching scheme, targeted towards improved cell performance and power integrity. We perform extensive analysis on each layout scheme and evaluate the timing/power benefits of the stitching scheme. Since the ground and power rails overlap in the T-M3D layouts with the folding scheme, we also present a design methodology for the power delivery network of folding T-M3D ICs to evaluate the impact of the T-M3D cell layout scheme on static power integrity. Compared to 2D ICs at iso-performance, stitching T-M3D ICs show a maximum of 6% power savings, 44% area savings with only 1% more static IR-drop in the 14nm technology node while folding T-M3D ICs undergo serious degradation in static power integrity, causing a reliability issue.

Original languageEnglish
Title of host publicationISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509060238
DOIs
StatePublished - 11 Aug 2017
Event22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017 - Taipei, Taiwan, Province of China
Duration: 24 Jul 201726 Jul 2017

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Conference

Conference22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017
Country/TerritoryTaiwan, Province of China
CityTaipei
Period24/07/1726/07/17

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