TY - GEN
T1 - Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity
AU - Ku, Bon Woong
AU - Song, Taigon
AU - Nieuwoudt, Arthur
AU - Lim, Sung Kyu
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/8/11
Y1 - 2017/8/11
N2 - Existing transistor-level monolithic 3D (T-M3D) standard cell layouts are based on the folding scheme, in which the pull-down network is simply folded and placed on top of the pull-up network. In this paper, we propose a new layout method, the stitching scheme, targeted towards improved cell performance and power integrity. We perform extensive analysis on each layout scheme and evaluate the timing/power benefits of the stitching scheme. Since the ground and power rails overlap in the T-M3D layouts with the folding scheme, we also present a design methodology for the power delivery network of folding T-M3D ICs to evaluate the impact of the T-M3D cell layout scheme on static power integrity. Compared to 2D ICs at iso-performance, stitching T-M3D ICs show a maximum of 6% power savings, 44% area savings with only 1% more static IR-drop in the 14nm technology node while folding T-M3D ICs undergo serious degradation in static power integrity, causing a reliability issue.
AB - Existing transistor-level monolithic 3D (T-M3D) standard cell layouts are based on the folding scheme, in which the pull-down network is simply folded and placed on top of the pull-up network. In this paper, we propose a new layout method, the stitching scheme, targeted towards improved cell performance and power integrity. We perform extensive analysis on each layout scheme and evaluate the timing/power benefits of the stitching scheme. Since the ground and power rails overlap in the T-M3D layouts with the folding scheme, we also present a design methodology for the power delivery network of folding T-M3D ICs to evaluate the impact of the T-M3D cell layout scheme on static power integrity. Compared to 2D ICs at iso-performance, stitching T-M3D ICs show a maximum of 6% power savings, 44% area savings with only 1% more static IR-drop in the 14nm technology node while folding T-M3D ICs undergo serious degradation in static power integrity, causing a reliability issue.
UR - http://www.scopus.com/inward/record.url?scp=85028586999&partnerID=8YFLogxK
U2 - 10.1109/ISLPED.2017.8009189
DO - 10.1109/ISLPED.2017.8009189
M3 - Conference contribution
AN - SCOPUS:85028586999
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
BT - ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017
Y2 - 24 July 2017 through 26 July 2017
ER -