Variable radix-2 multibit coding for 400 Mpixel/s DCT/IDCT of HDTV video decoder

Variable radix-2 multibit coding algorithm is presented and implemented in discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT). Variable radix-2 multibit coding means the 2^k signed digit (SD) representation of overlapped multibit scanning with variable shift method. SD represented by 2^k generates partial products, which can be easily implemented with shifters and adders. This algorithm is most powerful for the hardware implementation of DCT/IDCT with constant coefficient matrix multiplication. The VLSI architecture employing this algorithm shows superior performance for the parallel processing compared with the ROM-based distributed arithmetic architecture and ROM-based parallel multiplication. Since DCT/IDCT core needs matrix transposition, we propose an orthogonal transpose memory scheme that satisfies horizontal and vertical signal transfer. The simulation shows that the core is compatible with IEEE STD 1180-1990 and it runs at a rate of 400 Mpixels/s, which is up to 20 times as fast as design. The fabricated IDCT core runs at 54 MHz, features 28 latencies, consumes 0.9 W of power at 3.3 V and occupies 24 mm² in 0.6 μm triple metal CMOS technology for HDTV video decoder.