Vertical InGaAs tunnel-field-effect transistors by an electro-plating fin formation technique

Ji Min Baek; Hyeon Bhin Jo; Do Young Yun; In Geun Lee; Changmin Lee; Chan Soo Shin; Hyoungsub Kim; Dae Hong Ko; Tae Woo Kim; Dae Hyun Kim

doi:10.1016/j.sse.2019.107681

Vertical InGaAs tunnel-field-effect transistors by an electro-plating fin formation technique

Ji Min Baek, Hyeon Bhin Jo, Do Young Yun, In Geun Lee, Changmin Lee, Chan Soo Shin, Hyoungsub Kim, Dae Hong Ko, Tae Woo Kim, Dae Hyun Kim

School of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

In this letter, we introduce for the first time a nano-fin patterning technique that combines Au electro-plating and high-temperature InGaAs dry etching processes. We applied this technique to fabricate vertical homojunction InGaAs tunnel-field-effect-transistors (TFETs). An InGaAs fin width (W_fin) of 60 nm was implemented with excellent line-edge-roughness (LER). The fabricated vertical homojunction InGaAs TFETs with a gate length (L_g) of 100 nm exhibited excellent device characteristics, such as a minimum subthreshold swing (S_min) of 80 mV/decade, an on–off-ratio (I_ON/I_OFF) of 6.09 × 10² at V_DS = 0.3 V, and a drain induced barrier lowering (DIBL) of 208 mV/V at room temperature.

Original language	English
Article number	107681
Journal	Solid-State Electronics
Volume	164
DOIs	https://doi.org/10.1016/j.sse.2019.107681
State	Published - Feb 2020

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title = "Vertical InGaAs tunnel-field-effect transistors by an electro-plating fin formation technique",

abstract = "In this letter, we introduce for the first time a nano-fin patterning technique that combines Au electro-plating and high-temperature InGaAs dry etching processes. We applied this technique to fabricate vertical homojunction InGaAs tunnel-field-effect-transistors (TFETs). An InGaAs fin width (Wfin) of 60 nm was implemented with excellent line-edge-roughness (LER). The fabricated vertical homojunction InGaAs TFETs with a gate length (Lg) of 100 nm exhibited excellent device characteristics, such as a minimum subthreshold swing (Smin) of 80 mV/decade, an on–off-ratio (ION/IOFF) of 6.09 × 102 at VDS = 0.3 V, and a drain induced barrier lowering (DIBL) of 208 mV/V at room temperature.",

author = "Baek, {Ji Min} and Jo, {Hyeon Bhin} and Yun, {Do Young} and Lee, {In Geun} and Changmin Lee and Shin, {Chan Soo} and Hyoungsub Kim and Ko, {Dae Hong} and Kim, {Tae Woo} and Kim, {Dae Hyun}",

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doi = "10.1016/j.sse.2019.107681",

language = "English",

volume = "164",

journal = "Solid-State Electronics",

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TY - JOUR

T1 - Vertical InGaAs tunnel-field-effect transistors by an electro-plating fin formation technique

AU - Baek, Ji Min

AU - Jo, Hyeon Bhin

AU - Yun, Do Young

AU - Lee, In Geun

AU - Lee, Changmin

AU - Shin, Chan Soo

AU - Kim, Hyoungsub

AU - Ko, Dae Hong

AU - Kim, Tae Woo

AU - Kim, Dae Hyun

PY - 2020/2

Y1 - 2020/2

N2 - In this letter, we introduce for the first time a nano-fin patterning technique that combines Au electro-plating and high-temperature InGaAs dry etching processes. We applied this technique to fabricate vertical homojunction InGaAs tunnel-field-effect-transistors (TFETs). An InGaAs fin width (Wfin) of 60 nm was implemented with excellent line-edge-roughness (LER). The fabricated vertical homojunction InGaAs TFETs with a gate length (Lg) of 100 nm exhibited excellent device characteristics, such as a minimum subthreshold swing (Smin) of 80 mV/decade, an on–off-ratio (ION/IOFF) of 6.09 × 102 at VDS = 0.3 V, and a drain induced barrier lowering (DIBL) of 208 mV/V at room temperature.

AB - In this letter, we introduce for the first time a nano-fin patterning technique that combines Au electro-plating and high-temperature InGaAs dry etching processes. We applied this technique to fabricate vertical homojunction InGaAs tunnel-field-effect-transistors (TFETs). An InGaAs fin width (Wfin) of 60 nm was implemented with excellent line-edge-roughness (LER). The fabricated vertical homojunction InGaAs TFETs with a gate length (Lg) of 100 nm exhibited excellent device characteristics, such as a minimum subthreshold swing (Smin) of 80 mV/decade, an on–off-ratio (ION/IOFF) of 6.09 × 102 at VDS = 0.3 V, and a drain induced barrier lowering (DIBL) of 208 mV/V at room temperature.

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U2 - 10.1016/j.sse.2019.107681

DO - 10.1016/j.sse.2019.107681

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SN - 0038-1101

VL - 164

JO - Solid-State Electronics

JF - Solid-State Electronics

M1 - 107681

ER -

Vertical InGaAs tunnel-field-effect transistors by an electro-plating fin formation technique

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