VLSI architectures for CFAR detectors based on order statistics

In this paper, we propose new VLSI architectures for the order statistics (OS) constant false alarm rate (CFAR) detector and the modified OS-CFAR detectors such as the order statistics greatest of (OSGO) and the order statistics smallest of (OSSO) CFAR detectors. By transforming the OS-CFAR detection algorithm to a recursive algorithm, we derive efficient systolic array architectures to achieve good VLSI architectures. All the proposed architectures have several simple processing elements (PEs), a few communication links between adjacent PEs, and a high throughput rate suitable for real time processing.